Description: KHX8500D2T1K2/4G is a kit of two 256M x 64-bit 2GB (2048MB) DDR2-1066 CL5 SDRAM (Synchronous DRAM) memory modules, based on sixteen 128M x 8-bit DDR2 FBGA components per module. Total kit capacity is 4GB (4096MB). Each module pair has been tested to run at DDR2- 1066MHz at a latency timing of 5-5-5-15 at 2.2V - 2.3V. The SPD is programmed to JEDEC standard latency 800Mhz timing of 5-5-5-18 at 1.8V. Each 240-pin DIMM uses gold contact fingers and requires +1.8V. Specifications: Power supply : Vdd: 1.8V ± 0.1V, Vddq: 1.8V ± 0.1V Double-data-rate architecture; two data transfers per clock cycle Bidirectional data strobe(DQS) Differential clock inputs(CK and CK) DLL aligns DQ and DQS transition with CK transition Programmable Read latency 5 (clock) Burst Length: 4, 8 (Interleave/nibble sequential) Programmable Burst type (sequential & interleave) Timing Reference: 5-5-5-18 at +1.8V / 5-5-5-15 at +2.2V - 2.3V Edge aligned data output, center aligned data input Auto & Self refresh, 7.8us refresh interval (8K/64ms refresh) Serial presence detect with EEPROM High Performance Heat Spreader PCB : Height 1.180” (30.00mm), double sided component